Simulation programs are frequently used for testing integrated circuits. Integrated circuit production is characterized by high initial costs for the production of the first “copy” followed by low marginal costs for each successive copy. Testing of a design for an integrated circuit prior to production is almost imperative. There are major challenges in the area of functional verification of System-on-a-chip (SOC) design. Functional verification of the SOC design is necessary in order to verify that the integrated circuit functions are as expected and as designed. However, the design itself also needs to be tested for functional correctness. Currently, the SOC designs are implemented in High Level Hardware Specification languages such as Verilog. Verilog is a programming language defined by Open Verilog International (OVI) Corporation and now an Institute of Electrical and Electronic Engineers (IEEE) standard (IEEE-1364). The test benches for the SOC designs are also written in Verilog and are tested on Verilog simulation software.
In a conventional environment for functional verification of a system-on-a-chip design, a circuit design may be written in a hardware high level specification language, such as Verilog. The circuit design may be a very large design and may need to be tested on an emulator. The emulator may be utilized for design verification and validation since it is faster than a simulation software. The emulator may be interfaced to a host microprocessor. The test benches associated with the functional verification process performed by the emulator are often written in a language used for development of host software, such as C/C++. If the circuit design is written in a hardware high level specification language, such as Verilog, the test bench, associated with the circuit design may also be written in Verilog. However, to use the test bench with the emulator and the host microprocessor, the test bench may need to be written in C++.
It may be difficult and time consuming for the development of test benches written in both Verilog and C++. It may also be similarly difficult and time consuming for a test bench to be re-written from Verilog to C++. Another drawback is that it is difficult to maintain synchronization between the Verilog and C++ drivers as either one of them changes. As a result, both types of drivers, over a period of time, may diverge and create confusion in test bench development.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.